This invention relates to a buffer memory device for use in an information processing system comprising a cache memory between a data processing unit and a main memory.
In general, it is known in the art that a sequence of instruction data signals in a program tends to be continuously stored in consecutively numbered addresses of a main memory, which will be called a continuity of addresses for the instruction data signals while a sequence of operand data signals tends to be discontinuously dispersed or scattered in the main memory, which may be called a discontinuity of addresses for the operand data signals. Such instruction data signals and operand data signals are transferred from the main memory to a buffer memory device and stored in the cache memory at instruction data blocks and at operand data blocks.
A conventional buffer memory device of the type described comprises an instruction cache memory for memorizing the instruction data signals and an operand cache memory which is separated from the instruction cache memory and which memorizes the operand data signals. With this structure, it is possible to make each instruction block size of the instruction data blocks differ from each operand block size of the operand data blocks in consideration of the continuity and the discontinuity of the addresses for the instruction and the operand data signals, as mentioned above. This means that optimum block sizes can individually be selected for the instruction and the operand data blocks. Accordingly, the conventional buffer memory is effective to determine the instruction and the operand block sizes with reference to distribution of the addresses for the instruction and the operand data signals.
However, it is necessary to prepare both the instruction cache memory and the operand cache memory in the above-mentioned buffer memory device. Therefore, this buffer memory device is disadvantageous in that an amount of hardware essentially increases due to preparation of two cache memories.
Alternatively, a proposal has been offered about a buffer memory device comprising a common cache memory which memorizes both instruction data signals and operand data signals. In this structure, the common cache memory is loaded with both the instruction and the operand data signals at a common block size. In other words, no consideration is made about the continuity and the discontinuity of the addresses for the instruction and the operand data signals, respectively. Therefore, when the instruction and the operand data signals are memorized in the common cache memory at the common block size by neglecting the difference between the instruction and the operand block sizes, the common cache memory is not always effectively used for memorizing the instruction and the operand data signals.